Author: Jerry Long, Product Marketing Manager, EMA Design Automation
As technology advances, so does the complexity of the problems it exposes. Nowhere is
this more evident than in high-speed interface design. Timing issues previously deemed
insignificant are now impacting design schedules and can no longer be dealt with after
the fact. Design innovations such as double-data rate memory devices (DDR, DDRII, &
DDRIII), with their source synchronous capabilities and continuing speed improvements,
have increased the impact static timing issues have in resolving high-speed system
interface operation. Margins for data setup and hold requirements are tight which
leaves minimal room to secure an accurate data capture window. Faster edge rates also
magnify physical design effects, which cause signal integrity issues that require
additional settling time, shrinking timing margins further.
FPGA manufacturers like Altera® are keeping pace with devices that are extremely
register rich and offer advanced I/O features that directly support these high-speed
interface protocols. In addition, they provide intricate timing control capability
with fully programmable phase-locked loop networks. These features allow design of
memory controllers, data exchangers, and pipeline networks. To take full advantage
of these high-performance features and meet your timing requirements you must analyze
your available static timing options.
TimingDesigner® from EMA Design Automation is an ideal solution for high-speed,
multi-frequency designs like these where it is essential to accurately model and
analyze signal relationships between devices on a board or between embedded functions
on an ASIC or FPGA. It can evaluate comprehensive sets of timing alternatives and
provide direction to the most complex of timing challenges, enabling designers to
manage and monitor timing margins throughout the design process.
This application note will discuss the integration between TimingDesigner and
Altera Quartus® II which enables the exchange of critical timing data.
Quartus II Constraint Export – SDC generation capabilities within TimingDesigner
allows creation of constraint files that reference specific timing measurements
within your timing diagram. This ensures that the SDC constraints will mirror the
actual design intent and provides constraints directly to the Quartus II flow to
influence place & route.
Quartus II Post Place and Route Import – Altera’s TimeQuest® Timing Analyzer
provides incremental timing information of a placed and routed FPGA design. These
timing increments can be brought into TimingDesigner for visual display of post-place
and route timing analysis, allowing an update of the initial timing requirements
specification, and providing insight into how to correct any potential problems.
With this methodology designers can accurately control the place and route by
determining then exporting constraints from TimingDesigner, and get visual
verification of design success by importing post-place and route timing reports
for Altera FPGA devices.
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