Integrating EMA TimingDesigner with Xilinx and Altera Development Systems
When combined with advances in FPGA technologies for interface design efforts, EMA TimingDesigner® can simplify
design issues and provide advanced accurate control of virtually any interface. From simple SRAM interface protocols to high-speed
source synchronous interface protocols, TimingDesigner allows designers to identify potential timing problems early in the design
process and thereby providing the greatest opportunity to get the timing right the first time.
Detecting timing problems early in the design process not only saves time but also permits much easier implementation of design
alternatives. TimingDesigner allows you to create interactive timing diagrams for capturing interface specifications, analyze component
interface timing characteristics, and communicate design requirements among project engineering teams. In addition, TimingDesigner
contains features that allow exchange of critical timing data with Xilinx ISE™ and Altera Quartus® II tool sets, throughout the design
process. TimingDesigner can communicate place-and-route constraints that reference design specific timing measurements, and
allows direct use of post place-and-route timing information to provide visual verification of the interface signal relationships required
for desired FPGA interface operation. Integration with other FPGA tool sets such ispLEVER™ from Lattice®, Designer from Actel®,
and QuickWorks® from QuickLogic® is also planned for future releases of TimingDesigner.
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